1. Field of the Invention
This invention relates to analog phase frequency detecting apparatus, especially relates to an analog phase frequency detector that can rapidly lock the phase and frequency of the input signal.
2. Description of the Prior Art
The phase lock loop (PLL) is widely used in the high frequency circuit (especially in the communication system) to generate a signal that has the same frequency and phase as the input signal. In a PLL system (circuit), phase frequency detector is an important apparatus. It is used to detect the phase and frequency difference between the reference signal and the signal of voltage control oscillator (VCO). The block diagrams of prior art phase frequency detecting apparatus are shown in FIG. 1 and FIG. 2. In FIG. 1, It is a kind of digital phase frequency detector. In FIG. 2, It includes a phase detector and a switch.
In general, the phase frequency detecting apparatus is divided into two kinds digital and analog, the operational range of the digital phase frequency detecting apparatus is very large, so it is widely used in the frequency synthesizer. However, the digital phase frequency detector utilizes J-K flip flop (J-K FF) or tri-state phase frequency detector as a phase frequency detector. Since J-K flip flop (J-K FF) and tri-state phase frequency detector are digital circuits, their transistors will work in saturation or cut off region, and this will slow down the operation speed of the detector.
The other disadvantage of the digital phase frequency detector is illustrated below. If fin is the input frequency of the voltage control oscillator (VCO) and fref is the input frequency of the reference input signal, which are both being input to the digital phase frequency detector. As fin is much greater (or smaller) than fref, i.e., fin greater than  greater than fref, the output voltage level of the digital phase frequency detector is high (or low). In the other condition, if fin is only ten percents greater (or smaller) than fref, the output voltage level may continuously change between high voltage level and low voltage level.
Furthermore, in the digital phase frequency detector, because of the latch time of the flip-flop employed in the digital phase frequency detector, the operational speed of the digital phase frequency detector is confined, and the digital phase frequency detector can only operate in low speed.
As described above, the digital phase frequency detector can""t be used in some cases. So a certain type of analog phase frequency detector is evolved, for example, the block diagrams of the traditional analog phase frequency detector is illustrated in FIG. 2.
Though the traditional analog phase frequency detector try to raise its operational speed, its operational speed can""t be improved obviously. This is because strictly speaking it doesn""t contain a frequency detector. By the way, it is necessary to further improve the operation current of the phase detector that employed in the analog phase frequency detector. Particularly, the traditional analog phase frequency detector just has only one chance to lock the VCO (voltage controlled oscillator), so the locking capability is poor. A block diagram example of the prior art analog phase frequency detector is illustrated in FIG. 2. Accordingly, it is obvious that it discharges the loop filter at the beginning of each locking period and then charging with a constant current, thus it needs greater locking time at the occasion of higher input signal frequency. Since the prior art analog phase frequency detector has some limitations resulted from its circuit architecture, it is necessary to improve the prior art analog phase frequency detector to obtain better performance.
Because the traditional analog phase frequency detector has its limitations, it is advantageous to use an analog phase frequency detector composed of analog elements to detect the phase and frequency of a reference input signal with minimum current level. The analog phase frequency detecting apparatus according to one preferred embodiment of the present invention can be used to detect (lock) the phase and frequency of the input signals. The analog phase frequency detecting apparatus includes the following devices: the first frequency sensitive device, the second frequency sensitive device, the first DC component extracting means, the second DC component extracting means, the hysteresis comparator, the comparator, the loop filter, the phase detector, and the voltage controlled oscillator.
The first frequency sensitive device is used to amplify the reference input signal with a varying gain function responding to frequency of the reference input signal. The magnitude of the varying gain function varies corresponding to frequency of the reference input signal. The transfer characteristic curve of the first frequency sensitive device includes a monotonous curve within a linear mapping frequency range, and the first frequency sensitive device processes the reference input signal to generate a first amplified input signal.
The second frequency sensitive device is used to amplify an voltage controlled oscillator signal with the varying gain function responding to frequency of the oscillating signal. Besides, the second frequency sensitive device and the first frequency sensitive device are of the same architecture. So, the transfer characteristic curve of the second frequency sensitive device is same as that of the first frequency sensitive device, and the second frequency sensitive device processes the oscillating signal to generate a second amplified input signal.
The first DC component extracting means is used to extract the DC component of the first amplified input signal, and the working frequency range of the first DC component extracting means includes the linear mapping frequency range. The second DC component extracting means is used to extract the DC component of the second amplified input signal, and the working frequency range of the second DC component extracting means includes the linear mapping frequency range. In addition, the second DC component extracting means and the first DC component extracting means are of the same architectures.
The comparator is used to generate a frequency locking signal responding to difference between DC components of the first amplified input signal and the second amplified input signal and then adding a dc offset current which comes from the hysteresis comparator. In the other word, The magnitude of the frequency locking signal from the comparing means is proportional to the difference of frequency of the first amplified input signal and the second amplified input signal and having a dc offset current which comes from the hysteresis comparator.
The phase detector is used to generate a phase locking signal responding to the phase difference of the reference input signal and the oscillating signal. The hysteresis comparator is used to provide an intentional DC (direct component) offset current to the comparator to avoid the DC offset current (voltage) which are caused by process or layout in the frequency detecting apparatus. The loop filter is used for generating a voltage level responding to the frequency locking signal and the phase locking signal. The voltage controlled oscillator is used for generating the oscillator signal responding to the voltage level form the loop filter. For the purpose of ensuring the reference input frequency equals the oscillator frequency, the hysteresis comparator detects the output signals of comparator and then generates a feedback signal into the comparator to ensure there exits a chance to make the reference input frequency equals the oscillator frequency. As the reference input frequency equals the oscillator frequency the phase detector will generate a phase tracking signal to make the voltage controlled oscillator to have the same frequency and constant phase relationship to the reference input signal.
The first frequency sensitive means and the second frequency sensitive means include resonant circuit or filter circuit. The frequency sensitive circuits mentioned above can be chosen from a group of circuits consisting of: RC, LC, RC-CR, LC-CL, RC-LC circuits. Besides the first DC component extracting means and the second DC component extracting means includes rectifier (half wave rectifier or full wave rectifier). The comparing means utilized in the preferred embodiment of the present invention is a comparator including a differential amplifier.
However, a method for detecting frequency and phase of reference input signal is also disclosed herein, and the method mentioned above includes the following steps. The first step is to amplify the reference input signal and the voltage controlled oscillator signal with a varying gain function responding to frequency of the reference input signal and the oscillating signal respectively. The magnitude of the varying gain function varies corresponding to the frequency of its corresponding input signal. Then extract the direct current component of the reference input signal and the oscillating signal.
Next, generate a frequency locking signal responding to difference of direct current component of the reference input signal and the oscillating signal and then adding a dc offset current which comes from the hysteresis comparator. The magnitude of the frequency locking signal is proportional to difference of the direct current components of the reference input signal and the oscillating signal and having a dc offset current which comes from the hysteresis comparator. In other words, the magnitude of the frequency locking signal is proportional to the difference of the frequency of the reference input signal and the oscillating signal and having a dc offset current which comes from the hysteresis comparator. The frequency locking signal and the phase locking signal then input to the loop filter to generate a voltage level. Finally, the voltage controlled oscillator generates an oscillator signal responding to the voltage level, and keeps the frequency of the reference input signal and the oscillator signal are the same and has a constant phase relationship in these two signals.